Rising Star Faculty Award Program

Intel’s Rising Star Award (RSA) provides an award of $50,000 and networking support to faculty members who are early in their academic careers and show great promise as future academic leaders. The purpose of this Program is to help promote the careers of promising early career faculty members and to foster long term collaborative relationships with Intel.

Who Qualifies?

• Any full-time, tenured or tenure track (or equivalent) faculty member (including research faculty and / or faculty lecturers);
• With 4 years or less cumulative experience as a full-time university faculty (as of Sep ’24);
• From universities invited by Intel to participate in this Program;
• Nominated by appropriate department head (limited to 1 per university);
• Has made significant contributions to Research and Education that have the potential to be disruptive to the Semiconductor and Computing Industry in the areas outlined below;
• Has not previously been an RSA award recipient; and
• Has not been previously employed by Intel for longer than 2 years (excluding internships).

What Areas of Research is Intel Interested In for this Award?

Innovative and disruptive ideas in electrical engineering, computer science & engineering, material science, chemical engineering, mechanical engineering, and other STEM fields relevant to the semiconductor industry, which have potential to significantly advance semiconductor technologies and the future of computing.

Below are key topics of interest. In alignment with our growth strategy, Intel will look towards IDM 2.0 strategic technology areas as priorities in faculty interest although not exclusively:

Architecture: CPU microarchitecture features for general-purpose IPC (Instructions per Cycle); Advanced hardware-optimizers for CPU performance and power efficiency; Platform architecture; Domain-specific accelerators; New memory technologies in the scope of architecture systems optimization.

Artificial intelligence: More capable AI: enabling machines to exceed and augment human-level performance. Efficient/sustainable AI: scalable and efficient models and computing architectures, data and label-efficient learning; Future of work with AI: including common sense reasoning, cognition, voice and vision technologies; compiler & runtime research for agile efficient mapping of machine/deep learning; new applications & usages; Evaluating emerging applications and use cases: AI for semiconductor design and manufacturing; AI for optimization; Ethical AI."

Computer-Aided Design: Techniques spanning runtime optimization and tuning; Hyper-scale system-level modeling, analysis, and optimization for PnP, reliability, and security; SoC-level hardware-software co-design; Automation in system power-performance debug; System validation; Validation of security problems due to micro-architecture optimization; Use of big data analytics to improve validation; AMS validation and design.

Circuits: Monolithic & heterogeneous 2.5D/3D SoC/SiP; Scaled CMOS logic, memory and analog/mixed-signal circuits; Scalable special-purpose circuits & accelerators; Circuits for hardware security; Near-memory and in-memory compute for AI; Power delivery & management; Clocking circuits & NoC; Wireline and RF/wireless circuits; Advanced design tools, flows and methodologies.

Connectivity: Wireless & networking: Fusion of wireless sensing & communications (Beyond 5G, AI/ML for communication, passive & active radar, multi-use radios, self-awareness, human-machine interfaces, client & infrastructure); Programmable networks, infrastructure & microservices; Novel electrical interconnects; Photonic devices (modulators/photodetectors); Photonic packaging; Dense wavelength division multiplexing (DWDM) light sources (quantum dot/amplifiers).

Cryogenic Computing: Serves future needs across the quantum and cryogenic compute stack across: (i) quantum algorithms and error correction, (ii) cryogenic computing for both qubit control, read out and scaling, as well as high performance computing, and (iii) qubit device technology.

Devices: Energy efficient transistors (low voltage, power, and temperature), low voltage CMOS, 2D transistors, Ferro-Electrics for Energy Efficiency devices, “beyond-CMOS” (e.g., MESO (Magneto-Electric Spin-Orbit) transistor); Novel patterning methods & materials that extend Moore’s Law and/or the next generation of packaging technology; Device materials and reliability/stability for 3D stacking; Device parasitics, interconnects; Thermal issues of devices; DTCO (Design-Technology Co-Optimization); STCO (System Technology Co-Optimization); Analog devices for neural network applications.

Emerging Technology: Novel sensors & actuators; Emerging algorithms and analytics; Computational imaging, future of media & graphics, joint wireless sensing and communication, human-computer Interactions, privacy & security for sensors, autonomous systems & intelligence, emerging Edge/cloud usages, infrastructures and systems, ubiquitous compute, unconventional compute for Deep Learning / Neural Networks beyond standard Uarch, System Technology Optimization.

Manufacturing: Manufacturing, manufacturing supply chain / manufacturing metrology; Advances in manufacturing processes technology and digital manufacturing process automation, process standardization; Physical manufacturing process automation (Robotics, AR/VR); Smart manufacturing/Industry 4.0/Industrial IoT; Equipment productivity and modeling; Design for manufacturing and process technology co-optimization, autonomous digital Supply Chain based on simulations, digital twins, and large language models (Supply chain meta worlds); Resilient supply chain.

Materials & Patterning: Deposition, Etch, Materials Characterization, Integration, and Modeling of novel materials (3D, 2D, 1D, or QD), including (but not limited to): EUV photoresists, low-dimensional non-Cu conductors, high aspect ratio fill dielectrics and metals, and materials for packaging and die-stacking technologies; Off roadmap patterning, materials, processing, and fabrication techniques for Angstrom and sub-Angstrom technologies.

Programmable Systems: Field Programmable Gate Arrays (FPGA); Role of FPGAs in Heterogenous compute and AI compute; Spatial Compute; Novel FPGA architectures, including Coarse Grained Reconfigurable Arrays (CGRA); Novel programming models for FPGAs, including domain-specific overlays; Novel applications for in-network computing using FPGAs; Novel logic synthesis, placement, and routing; AI-powered Electronic Design Automation (EDA) for FPGAs, and 3D integration techniques targeting programmable logic.

Security: Hardware-, Software-, and Systems-Security; Privacy technologies and Confidential Computing; Cryptography; Security and Privacy of Machine Learning; Security Assurance and Formal Methods.

Software: Software for heterogeneous hardware; Machine Programming; Human Technology Interactions, ambient computing, and smart spaces; Unified programming models for distributed computing and AI across Cloud, Edge, and Client including function compute and microservices.

Systems Integration: Package Substrate and Interconnect Density Scaling; Cooling Solutions and Design Techniques to Mitigate Hotspots; Sockets with Ultra-High Thermal Design Power; Micro-Assembly of Heterogeneous Components; Fluxless Assembly; Power-Efficient and High-Performance Computing Platform Architectures; Power Delivery Systems, including Ultra-Efficient Power Conversion; Ultra-High-Bandwidth On-Package and System Interconnects; Novel 3D Architectures; High-Bandwidth On-Package and Off-Package Memory Topologies; Unique Packages & Boards for Emerging IoT, Automotive & Edge; Wireless Systems: 5G/6G and beyond.

The funder is particularly interested in candidates who are using innovative methods of teaching as well as those candidates who are on the forefront of increasing the participation of women and underrepresented minorities in STEM.

Application Instructions

Please submit:

1. A letter of nomination from the Dean or Chair that includes verification of the candidate’s start date. (Multiple applications within a school or college must be ranked by the Dean.) Please also include each listed item below as required for the funder’s nomination process:

• Name of nominee;
• How long have they been teaching in academia and where;
• General area of research the nominee is currently engaged in;
• Why you think this professor should be considered for an award, such as:
  • An overview of the professor’s publicly available research accomplishments during their time as a faculty member;
  • An overview of the professor’s proposed research agenda for the next five years;
  • How the professor is working to increase the participation of women and underrepresented minorities in science and engineering;
  • Innovative teaching methods the professor is using and how their methods and leadership is advancing education in technology and semiconductor development; and
  • Other awards the professor has received.

2. CV of the nominee

to limitedsubs@uw.edu by 5:00 PM Wednesday, May 8, 2024. Nominations are due to the sponsor 6/7/2024 if given the go‐ahead by the review committee.