In the present contribution we report on the electrical in-situ characterisation of p-type OTFTs in bottom gate – bottom contact (coplanar) geometry on highly doped <100> Si-substrates. A 150 nm thick layer of thermal silicon oxide with an optional polymer interface passivation layer serves as the gate dielectric whereas pentacene is chosen as the organic semiconductor (see Fig. 1). The OSC is evaporated on pre-fabricated model device structures by organic molecular beam epitaxy in a high vacuum system adapted to enable parallel in-situ electrical characterisation during the ultra-slow deposition of the semiconductor film. Thus, the experimental setup allows for the observation and analysis of the dynamics of channel formation and the dependence of electrical device characteristics on the thickness and morphology of the OSC-layer, which in turn reveal information about the OSC/dielectric-interface. Charge transport within the devices is investigated in direct correlation to the number of monolayers deposited. The evolution of transistor parameters is studied on a bi-layer dielectric of silicon oxide and PNDPE (poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) and compared to the behaviour on a pure silicon oxide dielectric. PNDPE is an intrinsically photo-patternable organic dielectric which serves as a passivation layer on top of the oxide, strongly reducing the interface trap density at the OSC/dielectric interface, as is clearly shown in our experimental data, and thus greatly improving the transistor performance. The layer morphology as well as the interface chemistry are characterised in-situ under ultra-high vacuum conditions by a variety of surface analytical techniques such as thermal desorption spectroscopy (TDS), Auger electron spectroscopy (AES), and X-ray photoelectron spectroscopy (XPS). This extensive nano-analytic characterization is complemented by ex-situ atomic force microscopy (AFM) measurements.